Semiconductor Engineering

Quality time?

System-Level Design sat down to discuss the future of verification with Olivier Haller, design verification team leader for STMicroelectronics’ functional verification group; Hillel Miller, functional ...
EDN

Test-bench generation tool simplifies IC design

TestBencher Pro VHDL and Verilog system-level test-bench generation software is said to dramatically simplify the process of creating and applying random bus transactions to RTL and gate-level IC and ...
EDN

Spotty support stymies broader acceptance of System Verilog, users say

SAN FRANCISCO — A handful of chip and systems companies said they are seeing real benefits from experiments and limited adoption of System Verilog, mainly in back-end design areas such as verification ...
Design-Reuse

Complex SoC Verification using ARM Processor

Technology evolution, in part, has enabled the transition of multi-million gate designs from large printed circuit boards to SoC (System on Chip). The major advantages of SoC include low cost per gate ...
Electronic Design

Testbench Automation Tool Provides Tight Links To Verilog Simulation

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...
Design-Reuse

Using Tcl to create a virtual component in Verilog

It has long been a goal to put realistic prototypes or models into system developer's hands as soon as possible. This has been accomplished with FPGAs, C language models and sometimes co-simulation ...
Business Insider

Compound Photonics Selects Velocity CAE Design-to-Test Tools From Alliance ATE

SANTA CLARA, CA, Nov. 05, 2019 (GLOBE NEWSWIRE) -- via NEWMEDIAWIRE -- Alliance ATE Consulting Group, Inc. announces today that Compound Photonics U.S. Corporation, a global leader and innovator of ...